1. Field of Invention
The present invention relates to a method of manufacturing a flash memory cell. More particularly, the present invention relates to a method of manufacturing an NAND-type flash memory cell that has a high coupling ratio and a low source/drain resistance. Additionally, when a programming or erasing operation is performed using the Fowler-Nordheim (F-N) tunneling effect, the operating voltage applied for proper working of the flash memory is lowered.
Description of Related Art
In general, the gate of a conventional flash memory has two layers, namely, a floating gate and a control gate. The floating gate layer fabricated from polysilicon material is used for the storage of electric charges. Normally, the floating gate is in a floating state because it does not have any direct connection with outside circuits. Above the floating gate is a control gate, which is used for controlling the storage and retrieval of data. Normally, the control gate is connected to a word line. The aforementioned floating gate and the control gate together constitutes a gate terminal structure, which is commonly referred to as a stacked gate. Since a flash memory can provide fast programming and erasing operations, it is a very popular type of erasable programmable read-only memory (EPROM). In general, the speed of a read or a write operation in a flash memory depends very much on the transferring speed of electrons from the floating gate to the source/drain terminal. For a flash memory structure having a high coupling ratio, the electric field necessary to initiate an F-N tunneling is small. In other words, the speed of transfer of electrons from the floating gate to the source/drain region is fast. Therefore, at present, the method to produce a flash memory structure that has a high coupling ratio is an important issue in semiconductor manufacture.
The conventional method of increasing coupling ratio in a flash memory includes increasing the overlapping area between the floating gate and the control gate, or decreasing the tunneling oxide area beneath the floating gate. However, according to the design rule, the flash memory must have a minimum size in the wafer in order for its layout to have the highest density. Under this condition, the overlapping area between the floating gate and the control gate above is limited, and therefore, a high coupling ratio is difficult to obtain. When the coupling ratio is low, a higher voltage must be supplied in order to operate the memory programming and erasing actions. For example, a voltage as high as 15V to 18V is needed. A high operating voltage makes any dimensional reduction of the flash memory very difficult. Besides, a thick gate oxide layer must be supplied to the peripheral MOS transistors to deal with the high voltage. For example, the thickness must be increased to about 200 .ANG. to withstand the high voltage. This will increase the difficulties in implementing the design.
In light of the foregoing, there is a need in the art to provide an improved flash memory cell structure.